SEALSQ partners with Lattice to integrate quantum-resistant TPM into FPGAs

SEALSQ Corp (NASDAQ: LAES) announced a collaboration with Lattice Semiconductor (NASDAQ: LSCC) to integrate TPM-based post-quantum security capabilities into select Lattice FPGA solutions. The partnership addresses growing demand for quantum-resistant technologies in mission-critical edge computing applications.

The collaboration combines SEALSQ's QS7001 and QVault TPM post-quantum capabilities with Lattice's FPGA platforms. A proof-of-concept integrates a Lattice secure FPGA with SEALSQ's post-quantum cryptography-based secure Root-of-Trust, demonstrating the technical feasibility of embedding TPM-based post-quantum cryptography directly into FPGA architectures.

"This collaboration perfectly illustrates SEALSQ's strategy of extending our leadership in post-quantum security beyond direct OEM sales," said Bernard Vian, General Manager of SEALSQ. The company continues to deliver secure chips directly to customers while leveraging expertise to empower strategic partners across the industry.

Eric Sivertson, Vice President of Security Business at Lattice Semiconductor, stated the partnership expands the company's quantum-capable portfolio of solutions. "By combining SEALSQ's QS7001 and QVault TPM based post‑quantum capabilities with Lattice's long-running leadership in secure, power‑efficient FPGA platforms, we further expand our quantum-capable portfolio of solutions," Sivertson said.

The companies will demonstrate the post-quantum security proof-of-concept at Embedded World 2026 from March 10-12 in Nuremberg, Germany. The demonstration will be available at Lattice's exhibit in Hall 4, Booth #528.

Both companies support industry efforts to advance post-quantum standards recommended by organizations such as NIST. The initiative aligns with the Year of Quantum Security 2026 launch in Washington, D.C., where stakeholders concluded quantum security represents an infrastructure and governance imperative.

You May Also Be Interested In